PATH:
usr
/
lib
/
firmware
/
qcom
/
glymur
/
Editing: cdsp_dtb.mbn
ELF ( ��4 4 � � �� ���� �� 8 8 � �� yp 8 g` ( g( qcom,glymur qcom,glymur board-id ,default_process-glymur-1.0-cdsp 6 � soc @ smem qcom,smem HCORE_TOP_CSR Y� c 0 v @ @ smp2p qcom,smp2p proc-info � � � smp2p-interrupts intr-01 � � � intr-02 � � � glink qcom,glink � proc-info � xport-smem-config edge-01 � � @ � � � N � � � edge-02 � � � � � N � � � xport-qmp-config edge-01 aop_cdsp � ! 9 S � h r 0 ipc_router qcom,ipc_router proc-info �cdsp � devcfg-glink-xals edge-01 �SMEM �apss �IPCRTR � �� � � � � � ipcc qcom,ipcc ipcc@3e03000 qcom,ipcc-protocol �� � �MPROC � � D ! " : ; < - . 7 8 @ ipcc@3e41000 qcom,ipcc-protocol �� � �COMPUTE_L0 � � $ 0 ! " - . @ ipcc@3e81000 qcom,ipcc-protocol �� � �COMPUTE_L1 � � % 0 ! " - . @ ipcc_legacy@32388004 �28 @ ipcc_legacy_cvp qcom,ipcc-legacy ) � � � � 0 timetick timer@323a2000 qcom,timetick �2: 9SystemTimer D$� O Y @ timer@323a3000 qcom,timetick �2:0 9WakeUpTimer D$� O Y @ pinctrl@f100000 ! qcom,glymur-pinctrl qcom,pinctrl � � i � p � v | � � � @ 2 3 � } �summary directconn0 directconn1 � �GPIOINTCDSP @ vdd_mxa qcom,rpmh-arc-regulator �/vcs/vdd_mxa /vcs/vdd_mx � � + Dmx.lvl W m } @ vdd_mxc qcom,rpmh-arc-regulator �/vcs/vdd_mxc � � + Dmxc.lvl W m } @ vdd_cx qcom,rpmh-arc-regulator �/vcs/vdd_cx � � + Dcx.lvl W m } @ vdd_nsp qcom,rpmh-arc-regulator �/vcs/vdd_nsp � � + Dnsp.lvl W m } @ vdd_nsp2 qcom,rpmh-arc-regulator �/vcs/vdd_nsp2 � � + Dnsp2.lvl W m } @ clock-controller@100000 qcom,gcc-glymur qcom,cc-glymur � � 0 @ P ` p � � � � � � � � 0 @ � � / � / � � �GCC_GPLL0_CM_PLL_TAYCAN_COMMON GCC_GPLL1_CM_PLL_TAYCAN_COMMON GCC_GPLL2_CM_PLL_TAYCAN_COMMON GCC_GPLL3_CM_PLL_TAYCAN_COMMON GCC_GPLL4_CM_PLL_TAYCAN_COMMON GCC_GPLL5_CM_PLL_TAYCAN_COMMON GCC_GPLL6_CM_PLL_TAYCAN_COMMON GCC_GPLL7_CM_PLL_TAYCAN_COMMON GCC_GPLL8_CM_PLL_TAYCAN_COMMON GCC_GPLL9_CM_PLL_TAYCAN_COMMON GCC_GPLL10_CM_PLL_ZONDA_COMMON GCC_GPLL11_CM_PLL_ZONDA_COMMON GCC_GPLL12_CM_PLL_ZONDA_COMMON GCC_GPLL13_CM_PLL_ZONDA_COMMON GCC_GPLL14_CM_PLL_TAYCAN_COMMON GCC_GPLL15_CM_PLL_TAYCAN_COMMON GCC_GPLL16_CM_PLL_TAYCAN_COMMON GCC_GPLL17_CM_PLL_TAYCAN_COMMON GCC_GPLL18_CM_PLL_TAYCAN_COMMON GCC_GPLL19_CM_PLL_TAYCAN_COMMON GCC_JBIST_CM_PLL_JBIST4_COMMON GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_RPUQ11_512_CL36L12_LE GCC_RPU_XPU4 � @ clock-controller@1f40000 % qcom,turing_cc-glymur qcom,cc-glymur X �� 2 � 2 2 2 2 0 2 @ 2 � @ 24 24� 6 � m �TCSR_TCSR_REGS TURING_CC_PLL TURING_CORE0_CORE0_CM_PLL_TAYCAN_COMMON TURING_CORE1_CORE1_CM_PLL_TAYCAN_COMMON TURING_CORE2_CORE2_CM_PLL_TAYCAN_COMMON TURING_CORE3_CORE3_CM_PLL_TAYCAN_COMMON TURING_CORE4_CORE4_CM_PLL_TAYCAN_COMMON TURING_CC_REG TURING_QDSP6SS_PLL_PLL_CM_PLL_TAYCAN_COMMON TURING_QDSP6SS_MXU_PLL_MXU_PLL_CM_PLL_TAYCAN_COMMON FUSE_CONTROLLER_SW_RANGE4 � @ clock-controller@32340000 ( qcom,turing_q6_cc-glymur qcom,cc-glymur �24 24@ @ 25 } �TURING_QDSP6SS_PLL_PLL_CM_PLL_TAYCAN_COMMON TURING_QDSP6SS_Q6V81NA_2_CC_REG TURING_QDSP6SS_QDSP6_QDSP6_Q6V81NA_2_ACD_MND_DCC � @ clock-controller@32348000 , qcom,turing_q6_hmx_cc-glymur qcom,cc-glymur �24� 24� @ 25 � �TURING_QDSP6SS_MXU_PLL_MXU_PLL_CM_PLL_TAYCAN_COMMON TURING_QDSP6SS_MXU_CC_MXU_CC_Q6V81NA_2_HMX_CC_REG TURING_QDSP6SS_QDSP6_MXU_QDSP6_MXU_Q6V81NA_2_ACD_MND_DCC � @ cxstmtrace@16000000 qcom,stmtrace � � x � cxstmcfg@10002000 qcom,stmcfg � � � � cxetb@11c05000 qcom,tmc ��P tpdm@11181000 qcom,tpdm � �tpdm_32 � � � � tpdm@11182000 qcom,tpdm � �tpdm_24 � � � � tpdm@11183000 qcom,tpdm �0 �tpdm_64 � � � � tpdm@11184000 qcom,tpdm �@ �tpdm_26 � � � � tpdm@11185000 qcom,tpdm �P �tpdm_79 � � � tpdm@11186000 qcom,tpdm �` �tpdm_27 � � � qdss $ �20 20 2< L2< � 2 @L2 @� �20 funnel@10041000 qcom,tfunnel � @ funnel@11c04000 qcom,tfunnel ��@ @ tpda@11188000 qcom,tpda �� null_tpda � .null_funnel @ systemcache@20400000 qcom,systemcache x � @ ` !� !� !� !� "� "� "� "� #� #� #� #� ( � �llcc_bcast_or_base llcc_bcast_and_base llcc0_base llcc1_base llcc2_base llcc3_base llcc4_base llcc5_base llcc6_base llcc7_base llcc8_base llcc9_base llcc10_base llcc11_base ddrss_regs_base ? @ O \ @ kernel_test_devices@0 � � interrupt-controller@10140000 test,interrupt-control � o � @ device1@f101000 qcom,test,singleton �Device region mapping with name � �device1 �test_reg_singleton ] �int1 device2@1011000 qcom,test,singleton ! �Device region mapping with index �device2 � ^ �int2 device3@0 qcom,test,singleton �Device with no region mapping �device3 � _ �int3 device4@1 qcom,test,not_compatible �Device not compatible �device4 � ` �zero int4 device5@1010000 qcom,test,non_singleton �Device region mapping with name � �device5 �test_reg_non_singleton sw @ core boot � mproc qmi qcsi qcom,qmi_qcsi_user_pd_config qmi_qcsi_ping_server_config � � @ debugtrace qcom,debugtrace � debugtools eic qcom,eic � � � Z version_tbl qcom,image_version_tbl_idx � err_qdi qcom,err_qdi �P 0 pd_mon pd_mon_restart qcom,pd_mon_restart = S rcinit qcom,rcinit_cfg rcinit_config_spinor g � �d � u0 � � � � � � � $ � @ � \ � x rcinit_config g � !4 � � � � � � � � � $ � @ � \ � x tms_diag qcom,tms_diag � ` systemcache qcom,systemcache-sw � � @ � ' diag qcom,cdsp_core_diagcfg diagcfg_cmd � �0 � $ $ 2$ K$ `$ ~$ �$ �$ �$ �$ $ $ 0$ M$ f$ �$! �$# �$$ �$% �$& �$' $( %$) diagcfg_param 7 M ` u � � � � � � � $ C a � v � � � � � 2 � � @ / H _ � r � � � � � � < � 8 � S � p �K � �� � � � & < U q � � � � � � , C \ @ y < � �Z � diagcfg_early_log � _ � � � � / diagcfg_f3_trace G ] � w qdsp_pm config qcom,config_data � � � l2ConfigRegRange � � � lpassRegRange � � � cores-array core0 � e � � � # core1 � } � � � # core2 � ~ � � � < # core3 � u � � � # core4 � � � � 4 # core5 � � � � � # core6 � � � � � 9 # core7 � � � � � : # core8 � � � � � ; # memories-array memory0 0 � clocks-array clock0 6 < D P/clk/cpu X a � clock1 6 < D Pturing_cc_q6ss_axis2_clk X a � clock2 6 < D Pturing_cc_vapss_axi_clk X a � clock3 6 < D Pturing_cc_tcms_clk X a � clock4 6 < D ! Pturing_cc_turing_wrapper_aon_clk X a � clock5 6 < D - Pturing_cc_turing_wrapper_bus_timeout_aon_clk X a � clock6 6 ' < D Pturing_cc_q6ss_ahbs_aon_clk X a � clock7 6 * < D Pturing_cc_vapss_ahbs_aon_clk X a � clock8 6 < D ! Pturing_cc_vapss_ahbs_timeout_clk X a � clock9 6 ! < D Pturing_cc_dma_ahbs_clk X a � clock10 6 " < D Pturing_cc_vapss_vma_ahbs_clk X a � clock11 6 / < D Pturing_cc_nspnoc_clk X a � clock12 6 0 < D Pturing_cc_nspnoc_ahbs_clk X a � clock14 6 3 < D Pturing_cc_ceng_ahbs_clk X a � clock15 6 F < D Pturing_cc_nspaux_xo_clk X a � clock16 6 E < D Pturing_cc_vapss_xo_clk X a � clock17 6 8 < D Pturing_cc_vapss_hcp_ahbs_clk X a � clock18 6 9 < D Pturing_cc_vapss_fint_prog_clk X a � clock19 6 : < D Pturing_cc_vapss_hcp0_clk X a � clock20 6 ; < D Pturing_cc_vapss_hcp1_clk X a � clock21 6 = < D Pturing_cc_vapss_mvr_prog_clk X a � clock22 6 > < D Pturing_cc_ubwcd_nspnoc_clk X a � clock23 6 b < D Pturing_cc_vapss_vma_clk X a � clock24 6 c < D Pturing_cc_dma_clk X a � clock25 6 p < D Pturing_cc_vapss_fint_clk X a � clock26 6 q < D Pturing_cc_vapss_hcp_clk X a � clock27 6 s < D ! Pturing_q6_hmx_cc_mxu_cc_core_clk X a � clock28 6 u < D Pturing_cc_ubwcd_clk X a � clock29 6 v < D Pturing_cc_vapss_mvr_clk X a � clock30 6 # < D Pturing_cc_ubwcd_ahbs_clk X a � clock31 6 I < D Pturing_cc_vapss_hcp_mdc_clk X a � clock32 6 L < D Pturing_cc_vapss_hcp_msf_clk X a � clock33 6 K < D Pturing_cc_ubwcd_msf_clk X a � clock34 6 M < D Pturing_cc_vapss_vma_msf_clk X a � clock35 6 N < D Pturing_cc_ubwcd_ipnoc_clk X a � clock36 6 O < D Pturing_cc_dma_msf_ubwcdip1_clk X a � clock37 6 P < D Pturing_cc_dma_msf_tcms_clk X a � busport-array busPort0 � j y � � � busPort1 � j @ y � � � � busPort2 � j y M � � � � busPort3 � j y O � � � � busPort4 � j y > � � Z � busPort5 � j y � � � busPort6 � % j � y � � � busPort7 � 3 j y � � � � busPort8 � 9 j y � 9 : I q � � � busPort9 � > j y ' � � � busPort10 � : j y � N K � e � busPort11 � ; j y � ; = I L q � e � busPort12 � < j y � N P � e � extroute-array extBusRoute0 � � % extBusRoute1 � � % extBusRoute2 � � % extBusRoute3 � � % extBusRoute4 � � % mipsroute-array mipsBwRoute0 � � % pwrDomain-array pwrDomain0 � � � 6 � � pwrDomain1 � �/core/cpu/latency � 6 � � pwrDomain2 � �VCS � 6 � � pwrDomain3 � �turing_cc_vapss_gdsc � 6 � � pwrDomain4 � �HMX � 6 � � features-array feature0 P � � feature1 � feature2 � feature3 �� � ��� feature4 � feature5 � feature6 � feature7 � feature8 � � ��� feature9 � ��� feature10 5�� � ��� feature11 /�� � ��� feature12 � feature13 � � � feature14 $=X � ��� feature15 �� � '� feature16 � feature17 � feature18 � feature19 � feature20 � feature21 � feature22 � feature23 � feature24 � feature25 � feature26 � feature27 � feature28 � feature29 � feature30 � feature31 � feature32 � feature33 � feature34 � feature35 � feature36 � feature37 � __symbols__ /soc /soc/ipcc/ipcc@3e03000 &/soc/ipcc/ipcc@3e41000 6/soc/ipcc/ipcc@3e81000 F/soc/ipcc_legacy@32388004 R/soc/timetick/timer@323a2000 ^/soc/timetick/timer@323a3000 j/soc/pinctrl@f100000 o/soc/vdd_mxa w/soc/vdd_mxc /soc/vdd_cx �/soc/vdd_nsp �/soc/vdd_nsp2 �/soc/clock-controller@100000 �/soc/clock-controller@1f40000 �/soc/clock-controller@32340000 �/soc/clock-controller@32348000 �/soc/funnel@10041000 �/soc/funnel@11c04000 �/soc/tpda@11188000 �/soc/systemcache@20400000 9 /soc/kernel_test_devices@0/interrupt-controller@10140000 /sw model compatible #address-cells #size-cells proc-name chip-info phandle core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets host-id fflags max-entries dest proc irq supported-hosts host remote-host fifo-size mtu-size irq-out qos-max-rate smem-id-desc smem-id-fifo cap channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name transport remote-ss ch-name options priority stack-size intents reg client protocol-name protocol-idx interrupt-parent interrupts #signals client-mapping offset out-mask timer-name timer-freq timer-num timer-interrupt ngpios width egpio qcom,strongpull gpio-controller #gpio-cells interrupt-types interrupt-names summary-targetproc global-ctxt-name regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id reg-names #clock-cells base_port num_ports atid sync_period tpdm_name tpda tpda_port dataset cmb_size dbg_regs pwrdbg_ctrl_reg port_stm tpda_name port_occupied_mask tpda_funnel_name llcc-common-reg llcc-lcp-reg channel-mode-check interrupt-controller #interrupt-cells message config service_id instance_id qdss_service_id eic_crash_enable eic_crash_type eic_crash_delay image_idx pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable image_id llccs scid-mapping-reg clients diag_cmd_request_f diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_stress_test_loopback diag_start_stress_test_f diag_get_cmd_reg_tbl diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_flow_control_count_base diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_get_time_api diag_stress_test_delayed_rsp diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_query_enable diag_get_drop_per diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_dsqb_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks min soc ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_legacy SystemTimer WakeUpTimer tlmm vdd_mxa vdd_mxc vdd_cx vdd_nsp vdd_nsp2 gcc turing_cc turing_q6_cc turing_q6_hmx_cc in_fun0_in_fun0_cxatbfunnel aoss_apb_fun0 null_tpda systemcache0 intc sw � �� y@ 8 g ( f� qcom,mahua qcom,mahua board-id ,default_process-mahua-1.0-cdsp 6 � soc @ smem qcom,smem HCORE_TOP_CSR Y� c 0 v @ @ smp2p qcom,smp2p proc-info � � � smp2p-interrupts intr-01 � � � intr-02 � � � glink qcom,glink � proc-info � xport-smem-config edge-01 � � @ � � � N � � � edge-02 � � � � � N � � � xport-qmp-config edge-01 aop_cdsp � ! 9 S � h r 0 ipc_router qcom,ipc_router proc-info �cdsp � devcfg-glink-xals edge-01 �SMEM �apss �IPCRTR � �� � � � � � ipcc qcom,ipcc ipcc@3e03000 qcom,ipcc-protocol �� � �MPROC � � D ! " : ; < - . 7 8 @ ipcc@3e41000 qcom,ipcc-protocol �� � �COMPUTE_L0 � � $ 0 ! " - . @ ipcc@3e81000 qcom,ipcc-protocol �� � �COMPUTE_L1 � � % 0 ! " - . @ ipcc_legacy@32388004 �28 @ ipcc_legacy_cvp qcom,ipcc-legacy ) � � � � 0 timetick timer@323a2000 qcom,timetick �2: 9SystemTimer D$� O Y @ timer@323a3000 qcom,timetick �2:0 9WakeUpTimer D$� O Y @ pinctrl@f100000 ! qcom,glymur-pinctrl qcom,pinctrl � � i � p � v | � � � @ 2 3 � } �summary directconn0 directconn1 � �GPIOINTCDSP @ vdd_mxa qcom,rpmh-arc-regulator �/vcs/vdd_mxa /vcs/vdd_mx � � + Dmx.lvl W m } @ vdd_mxc qcom,rpmh-arc-regulator �/vcs/vdd_mxc � � + Dmxc.lvl W m } @ vdd_cx qcom,rpmh-arc-regulator �/vcs/vdd_cx � � + Dcx.lvl W m } @ vdd_nsp qcom,rpmh-arc-regulator �/vcs/vdd_nsp � � + Dnsp.lvl W m } @ vdd_nsp2 qcom,rpmh-arc-regulator �/vcs/vdd_nsp2 � � + Dnsp2.lvl W m } @ clock-controller@100000 qcom,gcc-glymur qcom,cc-glymur � � 0 @ P ` p � � � � � � � � 0 @ � � / � / � � �GCC_GPLL0_CM_PLL_TAYCAN_COMMON GCC_GPLL1_CM_PLL_TAYCAN_COMMON GCC_GPLL2_CM_PLL_TAYCAN_COMMON GCC_GPLL3_CM_PLL_TAYCAN_COMMON GCC_GPLL4_CM_PLL_TAYCAN_COMMON GCC_GPLL5_CM_PLL_TAYCAN_COMMON GCC_GPLL6_CM_PLL_TAYCAN_COMMON GCC_GPLL7_CM_PLL_TAYCAN_COMMON GCC_GPLL8_CM_PLL_TAYCAN_COMMON GCC_GPLL9_CM_PLL_TAYCAN_COMMON GCC_GPLL10_CM_PLL_ZONDA_COMMON GCC_GPLL11_CM_PLL_ZONDA_COMMON GCC_GPLL12_CM_PLL_ZONDA_COMMON GCC_GPLL13_CM_PLL_ZONDA_COMMON GCC_GPLL14_CM_PLL_TAYCAN_COMMON GCC_GPLL15_CM_PLL_TAYCAN_COMMON GCC_GPLL16_CM_PLL_TAYCAN_COMMON GCC_GPLL17_CM_PLL_TAYCAN_COMMON GCC_GPLL18_CM_PLL_TAYCAN_COMMON GCC_GPLL19_CM_PLL_TAYCAN_COMMON GCC_JBIST_CM_PLL_JBIST4_COMMON GCC_AHB2PHY_SWMAN GCC_AHB2PHY_BROADCAST_SWMAN GCC_CLK_CTL_REG GCC_RPU_RPUQ11_512_CL36L12_LE GCC_RPU_XPU4 � @ clock-controller@1f40000 % qcom,turing_cc-glymur qcom,cc-glymur X �� 2 � 2 2 2 2 0 2 @ 2 � @ 24 24� 6 � m �TCSR_TCSR_REGS TURING_CC_PLL TURING_CORE0_CORE0_CM_PLL_TAYCAN_COMMON TURING_CORE1_CORE1_CM_PLL_TAYCAN_COMMON TURING_CORE2_CORE2_CM_PLL_TAYCAN_COMMON TURING_CORE3_CORE3_CM_PLL_TAYCAN_COMMON TURING_CORE4_CORE4_CM_PLL_TAYCAN_COMMON TURING_CC_REG TURING_QDSP6SS_PLL_PLL_CM_PLL_TAYCAN_COMMON TURING_QDSP6SS_MXU_PLL_MXU_PLL_CM_PLL_TAYCAN_COMMON FUSE_CONTROLLER_SW_RANGE4 � @ clock-controller@32340000 ( qcom,turing_q6_cc-glymur qcom,cc-glymur �24 24@ @ 25 } �TURING_QDSP6SS_PLL_PLL_CM_PLL_TAYCAN_COMMON TURING_QDSP6SS_Q6V81NA_2_CC_REG TURING_QDSP6SS_QDSP6_QDSP6_Q6V81NA_2_ACD_MND_DCC � @ clock-controller@32348000 , qcom,turing_q6_hmx_cc-glymur qcom,cc-glymur �24� 24� @ 25 � �TURING_QDSP6SS_MXU_PLL_MXU_PLL_CM_PLL_TAYCAN_COMMON TURING_QDSP6SS_MXU_CC_MXU_CC_Q6V81NA_2_HMX_CC_REG TURING_QDSP6SS_QDSP6_MXU_QDSP6_MXU_Q6V81NA_2_ACD_MND_DCC � @ cxstmtrace@16000000 qcom,stmtrace � � x � cxstmcfg@10002000 qcom,stmcfg � � � � cxetb@11c05000 qcom,tmc ��P tpdm@11181000 qcom,tpdm � �tpdm_32 � � � � tpdm@11182000 qcom,tpdm � �tpdm_24 � � � � tpdm@11183000 qcom,tpdm �0 �tpdm_64 � � � � tpdm@11184000 qcom,tpdm �@ �tpdm_26 � � � � tpdm@11185000 qcom,tpdm �P �tpdm_79 � � � tpdm@11186000 qcom,tpdm �` �tpdm_27 � � � qdss $ �20 20 2< L2< � 2 @L2 @� �20 funnel@10041000 qcom,tfunnel � @ funnel@11c04000 qcom,tfunnel ��@ @ tpda@11188000 qcom,tpda �� null_tpda � .null_funnel @ systemcache@20400000 qcom,systemcache X � @ ` !� !� !� !� "� "� "� "� ( � �llcc_bcast_or_base llcc_bcast_and_base llcc0_base llcc1_base llcc2_base llcc3_base llcc4_base llcc5_base llcc6_base llcc7_base ddrss_regs_base ? L @ \ i @ kernel_test_devices@0 � � interrupt-controller@10140000 test,interrupt-control � | � @ device1@f101000 qcom,test,singleton �Device region mapping with name � �device1 �test_reg_singleton ] �int1 device2@1011000 qcom,test,singleton ! �Device region mapping with index �device2 � ^ �int2 device3@0 qcom,test,singleton �Device with no region mapping �device3 � _ �int3 device4@1 qcom,test,not_compatible �Device not compatible �device4 � ` �zero int4 device5@1010000 qcom,test,non_singleton �Device region mapping with name � �device5 �test_reg_non_singleton sw @ core boot � mproc qmi qcsi qcom,qmi_qcsi_user_pd_config qmi_qcsi_ping_server_config � � @ debugtrace qcom,debugtrace � debugtools eic qcom,eic � � � Z version_tbl qcom,image_version_tbl_idx err_qdi qcom,err_qdi �P ' = pd_mon pd_mon_restart qcom,pd_mon_restart J ` rcinit qcom,rcinit_cfg rcinit_config_spinor t � �d � u0 � � � � � � � 1 � M � i � � rcinit_config t � !4 � � � � � � � � � 1 � M � i � � tms_diag qcom,tms_diag � ` systemcache qcom,systemcache-sw � � @ � ' diag qcom,cdsp_core_diagcfg diagcfg_cmd � �0 � $ %$ ?$ X$ m$ �$ �$ �$ �$ �$ $ +$ =$ Z$ s$ �$! �$# �$$ �$% �$& $' $( 2$) diagcfg_param D Z m � � � � � � � 1 P n � � � � � � � 2 � � % @ < U l � � � � � � � < � ( E � ` � } �K � Ȗ � � � 3 I b ~ � � � � � 9 P i @ � < � �Z � diagcfg_early_log � _ & � � � � < diagcfg_f3_trace T j � � qdsp_pm config qcom,config_data � � � l2ConfigRegRange � � � lpassRegRange � � � cores-array core0 � e � � 0 core1 � } � � 0 core2 � ~ � � < 0 core3 � u � � 0 core4 � � � 4 0 core5 � � � � 0 core6 � � � � 9 0 core7 � � � � : 0 core8 � � � � ; 0 memories-array memory0 = � clocks-array clock0 C I Q ]/clk/cpu e n � clock1 C I Q ]turing_cc_q6ss_axis2_clk e n � clock2 C I Q ]turing_cc_vapss_axi_clk e n � clock3 C I Q ]turing_cc_tcms_clk e n � clock4 C I Q ! ]turing_cc_turing_wrapper_aon_clk e n � clock5 C I Q - ]turing_cc_turing_wrapper_bus_timeout_aon_clk e n � clock6 C ' I Q ]turing_cc_q6ss_ahbs_aon_clk e n � clock7 C * I Q ]turing_cc_vapss_ahbs_aon_clk e n � clock8 C I Q ! ]turing_cc_vapss_ahbs_timeout_clk e n � clock9 C ! I Q ]turing_cc_dma_ahbs_clk e n � clock10 C " I Q ]turing_cc_vapss_vma_ahbs_clk e n � clock11 C / I Q ]turing_cc_nspnoc_clk e n � clock12 C 0 I Q ]turing_cc_nspnoc_ahbs_clk e n � clock14 C 3 I Q ]turing_cc_ceng_ahbs_clk e n � clock15 C F I Q ]turing_cc_nspaux_xo_clk e n � clock16 C E I Q ]turing_cc_vapss_xo_clk e n � clock17 C 8 I Q ]turing_cc_vapss_hcp_ahbs_clk e n � clock18 C 9 I Q ]turing_cc_vapss_fint_prog_clk e n � clock19 C : I Q ]turing_cc_vapss_hcp0_clk e n � clock20 C ; I Q ]turing_cc_vapss_hcp1_clk e n � clock21 C = I Q ]turing_cc_vapss_mvr_prog_clk e n � clock22 C > I Q ]turing_cc_ubwcd_nspnoc_clk e n � clock23 C b I Q ]turing_cc_vapss_vma_clk e n � clock24 C c I Q ]turing_cc_dma_clk e n � clock25 C p I Q ]turing_cc_vapss_fint_clk e n � clock26 C q I Q ]turing_cc_vapss_hcp_clk e n � clock27 C s I Q ! ]turing_q6_hmx_cc_mxu_cc_core_clk e n � clock28 C u I Q ]turing_cc_ubwcd_clk e n � clock29 C v I Q ]turing_cc_vapss_mvr_clk e n � clock30 C # I Q ]turing_cc_ubwcd_ahbs_clk e n � clock31 C I I Q ]turing_cc_vapss_hcp_mdc_clk e n � clock32 C L I Q ]turing_cc_vapss_hcp_msf_clk e n � clock33 C K I Q ]turing_cc_ubwcd_msf_clk e n � clock34 C M I Q ]turing_cc_vapss_vma_msf_clk e n � clock35 C N I Q ]turing_cc_ubwcd_ipnoc_clk e n � clock36 C O I Q ]turing_cc_dma_msf_ubwcdip1_clk e n � clock37 C P I Q ]turing_cc_dma_msf_tcms_clk e n � busport-array busPort0 � w � � � � busPort1 � w @ � � � � � busPort2 � w � M � � � � busPort3 � w � O � � � � busPort4 � w � > � � Z � busPort5 � w � � � � busPort6 � % w � � � � � busPort7 � 3 w � � � � � busPort8 � 9 w � � 9 : I q � � � busPort9 � > w � ' � � � busPort10 � : w � � N K � e � busPort11 � ; w � � ; = I L q � e � busPort12 � < w � � N P � e � extroute-array extBusRoute0 � � % extBusRoute1 � � % extBusRoute2 � � % extBusRoute3 � � % extBusRoute4 � � % mipsroute-array mipsBwRoute0 � � % pwrDomain-array pwrDomain0 � � � C � pwrDomain1 � �/core/cpu/latency � C � pwrDomain2 � �VCS � C � pwrDomain3 � �turing_cc_vapss_gdsc � C � pwrDomain4 � �HMX � C � features-array feature0 - P � � feature1 - � feature2 - � feature3 - �� � ��� feature4 - � feature5 - � feature6 - � feature7 - � feature8 - � � ��� feature9 - � ��� feature10 - 5�� � ��� feature11 - /�� � ��� feature12 - � feature13 - � � � feature14 - $=X � ��� feature15 - �� � '� feature16 - � feature17 - � feature18 - � feature19 - � feature20 - � feature21 - � feature22 - � feature23 - � feature24 - � feature25 - � feature26 - � feature27 - � feature28 - � feature29 - � feature30 - � feature31 - � feature32 - � feature33 - � feature34 - � feature35 - � feature36 - � feature37 - � __symbols__ $/soc (/soc/ipcc/ipcc@3e03000 3/soc/ipcc/ipcc@3e41000 C/soc/ipcc/ipcc@3e81000 S/soc/ipcc_legacy@32388004 _/soc/timetick/timer@323a2000 k/soc/timetick/timer@323a3000 w/soc/pinctrl@f100000 |/soc/vdd_mxa �/soc/vdd_mxc �/soc/vdd_cx �/soc/vdd_nsp �/soc/vdd_nsp2 �/soc/clock-controller@100000 �/soc/clock-controller@1f40000 �/soc/clock-controller@32340000 �/soc/clock-controller@32348000 �/soc/funnel@10041000 �/soc/funnel@11c04000 �/soc/tpda@11188000 /soc/systemcache@20400000 9 /soc/kernel_test_devices@0/interrupt-controller@10140000 /sw model compatible #address-cells #size-cells proc-name chip-info phandle core-top-csr-str tcsr-base mutex-offsets-data wonce-offsets host-id fflags max-entries dest proc irq supported-hosts host remote-host fifo-size mtu-size irq-out qos-max-rate smem-id-desc smem-id-fifo cap channel-name mailbox-area-size-bytes master-mailbox-size-bytes max-tx-pending-items is-master mailbox-desc-start host-name transport remote-ss ch-name options priority stack-size intents reg client protocol-name protocol-idx interrupt-parent interrupts #signals client-mapping offset out-mask timer-name timer-freq timer-num timer-interrupt ngpios width egpio qcom,strongpull gpio-controller #gpio-cells interrupt-types interrupt-names summary-targetproc global-ctxt-name regulator-name regulator-min-microvolt regulator-max-microvolt regulator-init-microvolt qcom,resource-name qcom,all-pd-regulator qcom,lpr-enable qcom,drv-id reg-names #clock-cells base_port num_ports atid sync_period tpdm_name tpda tpda_port dataset cmb_size dbg_regs pwrdbg_ctrl_reg port_stm tpda_name port_occupied_mask tpda_funnel_name num-channels llcc-common-reg llcc-lcp-reg channel-mode-check interrupt-controller #interrupt-cells message config service_id instance_id qdss_service_id eic_crash_enable eic_crash_type eic_crash_delay image_idx pd_timeout_exit_msec threshold_timeout_sec num_pdrs_log pd_mon_restart_enable pd_mon_dump_disable rcinit_term_err_fatal_enable rcinit_term_timeout rcinit_term_timeout_group_0 rcinit_term_timeout_group_1 rcinit_term_timeout_group_2 rcinit_term_timeout_group_3 rcinit_term_timeout_group_4 rcinit_term_timeout_group_5 rcinit_term_timeout_group_6 rcinit_term_timeout_group_7 rcinit_term_latency_enable image_id llccs scid-mapping-reg clients diag_cmd_request_f diag_dcm_cmd_reg_test_base diag_ulogdiag_processor_id diag_subsys_id_base diag_stress_test_loopback diag_start_stress_test_f diag_get_cmd_reg_tbl diag_legacy_health_count_base diag_get_max_req_pkt_len diag_delay_health_count_base diag_flow_control_count_base diag_subsys_mask_retrieval_base diag_f3_trace_set_config diag_tx_mode_config diag_get_time_api diag_stress_test_delayed_rsp diag_uimage_health_stats diag_start_stress_test_adv_f diag_health_stats_base diag_get_set_drain_param diag_set_drain_prop diag_health_report_config diag_get_set_client_settings diag_lock_buffer_api diag_query_enable diag_get_drop_per diag_instance_id_base diag_err_ulog_size diag_debug_ulog_size diag_cmd_ulog_size diag_data_ulog_size diag_qdss_ulog_size diag_ctrl_ulog_size diag_listener_ulog_size diag_sendbuf_dbg_ulog_size diag_dsqb_ulog_size diag_mpd_drain_timer_len diag_mpd_buf_commit_thresh_per diag_mpd_buf_drain_thresh_per diag_event_timer_len diag_event_rpt_pkt_len_size diag_event_rpt_pkt_size diag_drain_timer_len diag_event_send_max diag_event_heap_size diag_ctrl_send_buf_size diag_ctrl_read_buf_size diag_cmd_read_buf_size diag_event_sec_heap_size diag_dci_read_buf_size diag_rsp_heap_size diag_heap_size diag_f3_trace_buf_size diag_buf_size diag_rsp_alloc_retry_timer_len diag_mask_notify_timer_len diag_tx_sleep_threshold_default diag_tx_sleep_time_default diag_core_pd_drain_threshold diag_sio_timeout_timer_len diag_cmd_read_tout_timer_len diag_max_active_listeners diag_many_drain_per_mark diag_few_drain_per_mark diag_hdlc_pad_len diag_stress_task_sleep_complete diag_buf_commit_threshold diag_buffer_default_lock_state diag_deferrable_timer diag_deferrable_timer_ex diag_send_data_buf_size_max diag_min_send_data_size diag_msg_fmt_str_arg_size diag_event_rpt_pkt_len_size_nrt diag_event_rpt_pkt_size_nrt diag_event_send_max_nrt diag_event_timer_len_nrt diag_tx_sleep_threshold_nrt diag_tx_sleep_time_nrt diag_drain_timer_len_nrt diagbuf_commit_threshold_nrt diag_mpd_commit_thresh_nrt_per diag_uimage_drain_timer_len diag_uimage_buf_high_per_wm diag_uimage_f3_trace_buf_size diag_early_log_control diag_early_log_mask diag_early_event_mask diag_early_message_mask diag_f3_trace_control diag_f3_trace_detail_mask diag_f3_trace_version THREAD_NUMBER OVERHANG_VOTE_TIMEOUT_MS DEBUG_LEVEL baseAddr physAddr coreId pwrDomain coreClockInstances masterBusPortInstances slaveBusPortInstances numInstances memId clkId clkType clkCntlType clkName clkSrcId memoryId portConnection busClk regProgClocks icbarbMaster accessPort icbarbSlave masterPort slavePort pwrDomainName pwrDomainType intrReinitTrigger intrReinitDone securityClocks min soc ipcc_mproc ipcc_compute_l0 ipcc_compute_l1 ipcc_legacy SystemTimer WakeUpTimer tlmm vdd_mxa vdd_mxc vdd_cx vdd_nsp vdd_nsp2 gcc turing_cc turing_q6_cc turing_q6_hmx_cc in_fun0_in_fun0_cxatbfunnel aoss_apb_fun0 null_tpda systemcache0 intc sw � � h R � !� VU �^����;��ò�.���_Z_�� V�%@���,�a�,K��� �S(�t�o�g � wBH :���s��7�Oa ���eL�{g����` 0e0By��Bd ���u�8�f r\�[�::l�yc_U�8�!ET��h����o71 ��4F )��.џb �Ոw�`V��}���j�!֑0���d�Z~K 0��0�:�0 *�H�=0��1 0 UUS1,0*U#SECTOOLS SECP384R1 CURVE TEST ROOT010U San Diego10U QUALCOMM10U CDMA Technologies1200U )General Use Test Key 0 (for testing only)0 251231100433Z 451226100433Z0f1 0 UUS10U California10USecTools Test User10U SecTools10U San Diego0v0*�H�=+� "b �,ƣ�gh_� ��,�ZA��ꤘ��� f�lʳ��&����%�v��4��,9�� �q49�Pe���4�)Z�� � $���Uxe7���2�V��o0m0 U #0���w���DM2�@tXϙ�L�0 U 0 0 U �0U % 0 +0 U *�c ��tڙ�-M�� Z�0 *�H�=g 0d0QXف����`V+�^x �-J�H�S�F� ��k�3g%9*b s�!0jX�'�2��Zf�WE�o�)���P #^�E�̼��� �P��(�0��0�u�0 *�H�=0��1 0 UUS1+0)U"SECTOOLS SECP384R1 CURVE TEST ROOT10U San Diego10U QUALCOMM10U CDMA Technologies100.U 'General Use Test Key (for testing only)0 160321215215Z 360316215215Z0��1 0 UUS1,0*U#SECTOOLS SECP384R1 CURVE TEST ROOT010U San Diego10U QUALCOMM10U CDMA Technologies1200U )General Use Test Key 0 (for testing only)0v0*�H�=+� "b �T�}� �I%���O�[�H���p� ���]�� f�{�I/C#�9g@�q�Kx�?jE���yAs�Ԝh�'�$,���H pe���y�py�P5��`0^0 U #0�o�q�'�� s� ֟>q�b0 U ��w���DM2�@tXϙ�L�0U 0� 0 U 0 *�H�=i 0f1 � _H��9<�}��� ͣ�����b�:v࣮^6��+<�[ ��61 �ft���Wzcv�ž�$��ֱ(9� � @� n���)f��>�F�߲40��0�N�0 *�H�=0��1 0 UUS1+0)U"SECTOOLS SECP384R1 CURVE TEST ROOT10U San Diego10U QUALCOMM10U CDMA Technologies100.U 'General Use Test Key (for testing only)0 160321215211Z 360316215211Z0��1 0 UUS1+0)U"SECTOOLS SECP384R1 CURVE TEST ROOT10U San Diego10U QUALCOMM10U CDMA Technologies100.U 'General Use Test Key (for testing only)0v0*�H�=+� "b 3��x�~� �ҩ���/פ{���Py�jh`��7_�줎��j^��K1o�$�lTg ]���ء�[�SQ�q6 /�PZ����o�T:ާ�%i�1>}���`�<0:0 U o�q�'�� s� ֟>q�b0 U 0�0 U 0 *�H�=h 0e0u�(�C9�u���T(&�\�L<�t���Bv���ɿ�xJ��܀s6U�1 �H�/�h#8o&& �� ��> Ga���T�)��,$� ��W���������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
SAVE
CANCEL